Surface micromachining process for manufacturing electro-acoustic transducers, particularly ultrasonic transducers, obtained transducers and intermediate products

ABSTRACT

This invention relates to a surface micromachining process for manufacturing Electro-acoustic transducers, particularly ultrasonic transducers, said transducers comprising a silicon semiconductor substrate ( 1 ), on an upper surface of which one or more membranes ( 18 ) of resilient materials are supported by a structural layer ( 11 ) of insulating materiel, rigidly connected to said semiconductor substrate ( 1 ), said resilient material having a Young&#39;s modulus not lower than 50 GPa, said membranes ( 18 ) being metallised, said transducers including one or more lower electrodes ( 23, 25 ), rigidly connected to said semiconductor substrate ( 1 ), the process being characterised in that said structural layer ( 11 ) includes silicon monoxide. The invention further relates to an Electro-acoustic transducer, particularly an ultrasonic transducer, characterised in that the insulating material of the structural layer ( 11 ) is silicon monoxide. The invention also relates to an intermediate product for utilisation in said process for realising Electro-acoustic transducers, particularly ultrasonic transducers.

[0001] This invention relates to a surface micromechanical process formanufacturing Electro-acoustic transducers, particularly ultrasonictransducers, which enables an extremely high design flexibility to beachieved, in respect of the geometry and of the electrical andmechanical features of the device, as well as the maximum compatibilitywith the integration of control electronics directly on a substrateincorporating the transducers.

[0002] Furthermore, this invention relates to an Electro-acoustictransducer manufactured by the above process and to an intermediateproduct of said process.

[0003] It is known that the ultrasonic electrostatic capacitivetransducers represent a suitable alternative to the piezoelectrictransducers, since they are a solution of the problem of the 5 magnitudoorder of mismatch with the air acoustical impedance. Suchelectrostatical capacitive transducers, also designated as cMUT(Capacitive Micromachined Ultrasonic Transducers) are manufactured byplanar surface micromanufacturing techniques on silicon, therebyoffering the possibility to integrate the control electronics on thesame chip.

[0004] The above mentioned cMUT devices are specifically used forecographic image acquisition, even if their application is notexclusively restricted to such field. In particular, these transducersenable to carry out multi-frequency ecographic scanning as well as theacquisition of three-dimensional images in real time, with a scarcelyinvasive examination, such as an acoustic examination.

[0005] The micromanufactured capacitive transducers were firstlyrealised in 1998 at the Stanford University, California, where a searchteam directed by Khuri Yakub has been working in this field for aboutten years.

[0006] In particular, the relevant prior art includes U.S. Pat. No.5,619,476, upon which the preamble portions of claims 1, 47 and 60 arebased, disclosing three processes for manufacturing correspondingtransducers.

[0007] The first process provides for a silicon substrate upon which athermally grown sacrificial layer of silicon dioxide is realised. Inparticular, the thermal oxidation of the silicon broadly occurs attemperatures in the range of 900° C. to 1200° C. A layer of siliconnitride is then deposited on said sacrificial layer by a low pressurechemical vapour deposition procedure or LPCVD procedure, which isgenerally carried out at temperatures in the range of 700° C. to 900° C.Lastly, the sacrificial layer is partially removed by an etchingoperation which should be carefully timed in order to control themembrane size. At the end of the process, one obtains transducerscomprising membranes of silicon nitride supported by portions of thesilicon dioxide sacrificial layer that have not been removed by theetching operation.

[0008] A second process provides for realising by a deposition proceduregrooves of silicon nitride aimed at defining the borders of the silicondioxide sacrificial layer areas, in order both to realise membranes ofarbitrary shapes and to make the chemical etch timing less critical. Atthe end of the process, one obtains transducers comprising membranes ofsilicon nitride rigidly supported by the silicon nitride grooves. Inparticular, since the subsequently deposited layers of silicon nitrideraise adhesion problems when the deposition is carried out at lowtemperature, it is apparent that the concerned silicon nitride should bedeposited also in this second process by means of a LPCVD procedure athigh temperature.

[0009] A third process provides for a glass substrate upon which apolyamide sacrificial layer is realised. A layer of silicon nitride isdeposited upon said sacrificial layer by means of a plasma enhancedchemical vapour deposition on PECVD procedure, which necessarily takesplace at low temperatures, in the range of 200° C. to 400° C., in ordernot to burn the polyamide. Lastly, the sacrificial layer in partiallyremoved by means of a carefully timed chemical etching operation aimedat controlling the membrane size. At the end of the process, one obtainstransducers comprising silicon nitride membranes supported by portionsof the polyamide sacrificial layer not removed by said etchingoperation. The known prior art also includes document 1. Ladabaum, X.Jin, H. T. Soh, A. Atalar and B. T. Khuri Yakub, “Surface MicromachinedCapacitive Ultrasonic Transducers”, IEEE Trans. Ultrason. Ferroelect.Freq. Contr., Vol 45, pp. 678-690, May 1998, that, in the assumption ofa theoretical model representing the Electro-acoustic behaviour of anultrasonic transducer, discloses a manufacturing process similar to theprocess described in U.S. Pat. No. 5,619,476.

[0010] The known prior art further includes U.S. Pat. No. 5,870,351 thatdiscloses a process for manufacturing a large band ultrasonic transducercomprising a plurality of membranes of different geometric shapeselectrically connected with one another. The disclosed manufacturingprocess is similar to the first process described in U.S. Pat. No.5,619,476, with the possible variation in which a plastic material ringis provided for limitation of the sacrificial layer areas correspondingto the membranes.

[0011] Further included in the known prior art is U.S. Pat. No.5,894,452 disclosing a process for manufacturing an ultrasonictransducer adapted to operate in submerged condition in a fluid. Themanufacturing process as disclosed is again analogous to the firstprocess described in U.S. Pat. No. 5,619,476, with addition of a furtherstep aimed at sealing the vias by CVD deposition of a further siliconnitride layer. In this process, the size of the concerned vias appearsto be particularly critic, in order to guarantee that no silicon nitrideis introduced under the membranes during the sealing step.

[0012] The known prior art also includes U.S. Pat. No. 5,982,709 thatdiscloses a process for manufacturing an ultrasonic transducer whereinthe membranes and their supports are formed during the same siliconnitride deposition and wherein the material deposited for sealing thevias is prevented from reaching the area underlying the membranes bydefining the vias only in correspondence to tanks and to complexconnection channels between the vias and the underlying areas of themembranes. This manufacturing process is analogous to the second processdescribed in U.S. Pat. No. 5,619,476, with the possible variation of apolysilicon sacrificial layer, aimed at increasing the selectivity ofthe etching solution. Also in this process, the size of the vias appearsto be particularly critic.

[0013] Lastly, the known prior art also includes PCT Application No. WO00/72631, that disclosed an acoustic transducer and a process formanufacturing it similar to the previously mentioned ones, in which thelower metallisation is realised in the chambers formed just under themembranes. The described manufacturing process uses aluminium or siliconoxide deposited at low temperature as sacrificial materials. Thematerials utilised for making the electrodes are aluminium or copper ortungsten having low resistivity.

[0014] The processes disclosed in the prior art, particularly in U.S.Pat. No. 5,619,476 have some drawbacks.

[0015] In the first place, the sacrificial layer, the membranes and themembrane supports are realised with only two different materials. Thismakes the selection of the process parameters and of the chemicaletching solutions particularly critic for the obtainment of highselectivities, in order to control the geometry and the electrical andmechanical features of the process. Obviously, these critical aspects ofthe process make the latter particularly complex and expensive.

[0016] Furthermore, many processing steps are carried out at hightemperatures, no lower than 600-700° C., thereby making the selectionand the control of the process parameter additionally critic andreducing compatibility of the concerned process with the integration ofcontrol electronics on the same substrate on which the transducers arerealised.

[0017] In addition, the utilised materials and the processingtemperatures cause an irregular planarity of the manufactured devices,thereby causing the establishment of significant parasitic capacitancesin the transducers themselves, which, in turn, jeopardise their correctoperation modes.

[0018] Furthermore, the third process as proposed by the U.S. Pat. No.5,619,476 appears to be quite inefficient, due to the fact thatpolyamide is quite unsuitable as a support layer. In fact, this materialhas a quite low Young's modulus and therefore, a polyamide support forthe concerned membranes would track the vibrations thereof, by absorbingthem and generating beat effects. In addition, the intrinsic compressionstress of the silicon nitride membranes deposited by a PECVD depositionprocedure at low temperature appears to be extremely high, therebyfurther making the concerned membranes highly inefficient, while themembranes themselves should have a small intrinsic tensile stress. Onthe other hand, should it be desired to use silicon nitride layers assupports of the membranes (and possibly as grooves of the sacrificiallayer), a further drawback would be encountered caused by the lowadhesion of the subsequently deposited membranes of silicon nitride; infact, the requirement to have high temperatures in order to obtain agood adhesion could not be fulfilled because, in stead, low processtemperatures are necessarily required in order to prevent the polyamidefrom burning. In effect, the just above discussed problems in respect ofthe third process have resulted into elimination of such approach fromall above mentioned known prior art subsequent to U.S. Pat. No.5,619,476.

[0019] Also in PCT Application No. WO/0072631 the sacrificial layers ofaluminium or silicon oxide deposited at low temperature raise thedrawbacks due to the poor selectivity of the chemical etching operationsneeded for their elimination, thereby making the manufacturing processcritic and, consequently, complex and expensive.

[0020] Furthermore, the residual mechanical stress level of themembranes of a transducer manufactured by the above discussed knownprocesses is particularly high and hardly controllable, since itnoticeably depends on the proportion between silicone (SiH₄) and ammonia(NH₃) and anyway it cannot be handled in arbitrary manner.

[0021] Lastly, the membranes have high gradients of mechanical stress,due to the fact that the membranes themselves have apertures or vias inthe silicon nitride layer, as needed to permit the sacrificial layer tobe etched. U.S. Pat. No. 5,982,709 proposes a solution to overcome suchproblem by means of a complex and expensive definition of patternscomprising grooves and intricate channels.

[0022] It is an object of this invention, therefore, to provide asurface micromechanical process for manufacturing Electro-acoustictransducers which enable to achieve in simple, inexpensive and reliableway a high design flexibility, in respect of the geometry as well as theelectrical and mechanical features of the device, together within themaximum compatibility with the integration of control electronicsdirectly on the same substrate incorporating the transducers.

[0023] Another object of this invention is to provide a process of theabove kind to maximise the planarity of manufactured transducers and toenable a dramatic reduction of the parasitic capacitances to be achievedin such devices.

[0024] Such objects are realised by using silicon monoxide deposited atlow temperature, as a structural support layer for the membranes.

[0025] A further object of this inventions to provide a process of theabove kind which enables a substantially arbitrary reduction to beobtained in the residual mechanical stresses in the membranes of themanufactured transducers.

[0026] A still further object of this invention is to provide a processof the above kind which enables a dramatic reduction of the mechanicalstress gradients in the membranes as caused by presence of vias therein.It is specific subject-matter of this invention to realise a surfacemicromachined process for manufacturing Electro-acoustic transducers,particularly ultrasonic transducers, said transducers comprising asilicon semiconductor substrate, on an upper surface of which one ormore membranes of resilient materials are supported by a structurallayer of insulating material, rigidly connected to said semiconductorsubstrate, said resilient material having a Young's modulus not lowerthan 50 GPa, said membranes (18) being metallised, said transducersincluding one or more lower electrodes, rigidly connected to saidsemiconductor substrate, the process comprising the following steps:

[0027] A. providing a silicon semiconductor substrate,

[0028] B. realising an intermediate product comprising:

[0029] a sacrificial layer, and

[0030] a structural layer of insulating material,

[0031] rigidly connected to an upper surface of said siliconsemiconductor substrate, the surfaces of said sacrificial layer and ofsaid structural layer not in contact with said substrate beingsubstantially co-planar,

[0032] C. depositing a layer of said resilient material on saidsacrificial layer and on said structural layer, and

[0033] D. releasing said membranes of said resilient material byremoving said sacrificial layer from the product obtained according tosaid step C.,

[0034] said process being characterised in that said structural layerincludes silicon monoxide.

[0035] Preferably according to this invention, all of the steps of theprocess are carried out at temperatures no higher than 600° C. and evenmore preferably at temperatures no higher than 530° C.

[0036] Preferably according to this invention, said resilient materialhas a value of the Young's modulus no lower than 100 GPa.

[0037] Even more preferably according to this invention, said resilientmaterial comprises silicon nitride.

[0038] According to this invention, said resilient material can comprisecrystalline silicon.

[0039] Preferably according to this invention, said sacrificial materialcomprises chromium.

[0040] Alternatively according to this invention, said sacrificialmaterial comprises an organic polymer selected among the groupcomprising polyamides and polymers of benzocyclobutene and itsderivatives, preferably polyamide and even more preferablyN-methyl-2-pyrolidone.

[0041] According to this invention, said step D can comprise thefollowing successively ordered sub-steps:

[0042] D.1 realising one or more apertures or vias on said layer ofresilient material, adapted to enable accessing the sacrificial layerfrom outside, and

[0043] D.2 thermally treating by annealing the product obtainedaccording to said step C.

[0044] Further according to this invention, during execution of saidsub-step D.2, the product obtained according to said step C is heated toa temperature in the range of 490° C. to 530° C.

[0045] Again according to this invention, said sub-step D.2 can be of aduration adapted to completely eliminate the organic polymer existing inthe product obtained according to said step C.

[0046] Still according to this invention, said step D can furthercomprise, indifferently before or after said sub-step D.1 or D.2, thefollowing sub-step:

[0047] D.3 chemically etching said sacrificial layer.

[0048] Still according to this invention, said sub-step D.3 can compriseimaging the product in a wet etching solution for etching chromium.

[0049] Alternatively according to this invention, said sub-step D.3 cancomprise imaging the product obtained according to said step C in asolution comprising sulphuric acid (H₂SO₄) and possibly hydrogenperoxide (H₂O₂), in which case said solution is a solution 7:3 ofsulphuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂).

[0050] Further according to this invention, when said sub-step D.3 issubsequent to said sub-step D.2, said step D can further comprise, aftersaid sub-step D.3, the following sub-step:

[0051] D.4 thermally treating by annealing the product obtainedaccording to said step D.

[0052] Also according to this invention, during execution of saidsub-step D.4, the product obtained according to said step C can beheated to a temperature in the range of 490° C. to 530° C.

[0053] Preferably according to this invention, the total duration of theannealing operation for the product obtained according to said step C isadapted to make the intrinsic compression stress of the membranes (18)no higher than 10 MPa.

[0054] Again according to this invention, the total duration of theannealing operation for the product obtained according to said step C isadapted to make the intrinsic tensile stress of the membranes comprisedin the range of 10 MPa to 50 MPa.

[0055] Further according to this invention, said vias can be external tothe locations of said membranes and can be positioned at a distancetherefrom adapted to introduce substantially negligible stressgradients, said sacrificial layer comprising channels to connect thepositions of said vias to the locations of said membranes.

[0056] Still according to this invention, said step B can comprise thefollowing successively ordered sub-steps:

[0057] B.1 depositing a chromium comprising layer on said upper surfaceof the semiconductor substrate,

[0058] B.2 defining configurations or patterns in said chromiumcomprising layer by realising cavities in said chromium comprisinglayer, and

[0059] B.3 filling said cavities in said chromium comprising layer bydepositing silicon monoxide therein.

[0060] Alternatively according to this invention, said step B cancomprise the following successively ordered sub-steps:

[0061] B.1 applying a polyamide comprising layer upon said upper surfaceof the semiconductor substrate,

[0062] B.2 defining configurations or patterns in said layer polyamidecomprising layer by realising cavities (10) in said in said polyamidecomprising layer, and

[0063] B.3 filling said cavities in said polyamide comprising layer bydepositing silicon monoxide therein.

[0064] Still according to this invention, during said sub-step B.3, thesilicon monoxide can be deposited by thermal evaporation.

[0065] Further according to this invention, said sub-step B.2 cancomprise an optical lithographic process performed on said chromiumcomprising layer by utilising a masking layer of photographicallypatterned optical resist and a wet chemical etching of the chromium.

[0066] Alternatively according to this invention, said sub-step B.2 cancomprise a dry reactive ion etching (RIE) operation performed on saidpolyamide comprising layer by utilising a masking layer ofphotolithographically patterned optical resist.

[0067] Still according to this invention, said step B can furthercomprise, after said sub-step B.3, the following sub-steps:

[0068] B.4 chemically etching said silicon monoxide by utilising a wetetching process,

[0069] B.5 removing said optical resist.

[0070] Alternatively according to this invention, said step B canfurther comprise, after said sub-step B.3, the following sub-step:

[0071] B.4 removing the silicon monoxide deposited upon said opticalresist by means of a lift off process.

[0072] Still according to this invention, said sub-step B.4 can alsocomprise dissolving said optical resist by means of an acetone andultrasound dissolving process.

[0073] Alternatively according to this invention, said step B cancomprise the following successively ordered sub-steps:

[0074] B. 1 depositing a silicon monoxide comprising layer on said uppersurface of the semiconductor substrate,

[0075] B.2 defining configurations or patterns in said silicon monoxidecomprising layer,

[0076] B.3 applying a polyamide comprising layer upon said upper surfaceof the semiconductor substrate, provided with silicon monoxide,

[0077] B.4 performing a chemical-mechanical polishing operation adaptedto realise said intermediate product.

[0078] Still according to this invention, during said sub-step B.1, thesilicon monoxide can be deposited by thermal evaporation.

[0079] Further according to this invention, said sub-step B.2 cancomprise a dry reactive ion etching (RIE) operation performed on saidsilicon monoxide comprising layer by utilizing a masking layer ofphotolithographically patterned optical resist.

[0080] Preferably according to this invention, during said step C, saidresilient material is deposited by a plasma enhanced chemical vapourdeposition process (PECVD).

[0081] Still according to this invention, said process can furthercomprise, after said step D, the following step:

[0082] E. closing said vias by

[0083] deposition of silicon monoxide adapted to fill up said vias,

[0084] optical lithography, and

[0085] RIE etching of the silicon monoxide deposited on said membranes.

[0086] Still according to this invention, during said step E, thesilicon monoxide can be deposited by thermal evaporation.

[0087] Further according to this invention, said process can alsocomprise, before said step B, the following step:

[0088] F. realising a lower electrode on the upper surface of thesemiconductor substrate in positions corresponding to each area in whichsaid membranes are realised during said step D.

[0089] Again according to this invention, said step F comprises thefollowing sub-steps:

[0090] F.1 depositing an insulating layer on the upper surface of thesemiconductor substrate,

[0091] F.2 depositing a conductive layer upon said insulating layer,

[0092] F.3 defining configurations or patterns in said conductive layer.

[0093] Again according to this invention, said insulating layer cancomprise thermal silicon dioxide SiO₂, said conductive layer cancomprise evaporation deposited chromium, and said sub-step F.3 cancomprise an optical lithographic process performed on said conductivelayer by utilising a masking layer formed by a photolithographicallypatterned optical resist and a chemical wet etching of the chromium.

[0094] Further according to this invention, said step F can furtherrealise a film for protection of said lower electrodes.

[0095] Still according to this invention, said protection film isrealised by growing a film of silicon nitride SiN by means of a PECVDtechnique.

[0096] Alternatively according to this invention, said process canfurther comprise the following step:

[0097] F. realising one or more lower electrodes by metallisation of alower surface of said semiconductor substrate.

[0098] Again according to this invention, said process can furthercomprise the following step:

[0099] G. metallising said membranes.

[0100] Preferably according to this invention, said siliconsemiconductor substrate is a p-type doped silicon substrate having aresistivity no higher than 1 Ω.cm, preferably no higher than 2 Ω.cm.

[0101] Still according to this invention, said silicon monoxidecomprising structural layer has a thickness in the range of 100 nm to1000 nm, preferably in the range of 400 nm to 600 nm, and said membranesof said resilient material can have a thickness no higher than 1000 nm,preferably no higher than 600 nm.

[0102] It is further subject-matter of this invention the realisation ofan Electro-acoustic transducer, particularly an ultrasonic transducer,comprising a silicon semiconductor substrate, on an upper surface ofwhich one or more membranes of resilient materials are supported by astructural layer of insulating material, rigidly connected to saidsemiconductor substrate, said resilient material having a Young'smodulus not lower than 50 GPa, said membranes being metallised, saidtransducer including one or more lower electrodes, rigidly connected tosaid semiconductor substrate, said transducer being characterised inthat said insulating material is silicon monoxide.

[0103] Preferably according to this invention, said resilient materialhas a value of the Young's modulus no lower than 100 GPa.

[0104] Even more preferably according to this invention, said resilientmaterial comprises silicon nitride.

[0105] Further according to this invention, said resilient material cancomprise crystalline silicon.

[0106] Preferably according to this invention, the membranes of thetransducer have an intrinsic compression stress no higher than 10 MPa.

[0107] Still according to this invention, said membranes of thetransducer have an intrinsic tensile stress in the range of 10 MPa to 50MPa.

[0108] Again according to this invention, said structural layer of thetransducer can have a thickness in the range of 100 nm to 1000 nm,preferably in the range of 400 nm to 600 nm, and said membranes of thetransducer can have a thickness no higher than 1000 nm, preferably nohigher than 600 nm.

[0109] Preferably according to this invention, said one or more lowerelectrodes are realised on the upper surface of said semiconductorsubstrate in positions corresponding to each of said areas underlyingsaid membranes.

[0110] Further according to this invention, said transducer can furthercomprises an insulating layer, underlying said lower electrodes, on theupper surface of said semiconductor substrate.

[0111] Still according to this invention, said insulating layer cancomprise silicon dioxide SiO₂ and said conductive layer can comprisechromium.

[0112] Again according to this invention, said transducer can furthercomprise a film for protection of said lower electrodes.

[0113] Further according to this invention, said protection film cancomprise silicon nitride SiN.

[0114] Alternatively according to this invention, said one or more lowerelectrodes are realised by means of a metallised layer on said lowersurface of the semiconductor layer.

[0115] It is further subject-matter of this invention an intermediateproduct for realising Electro-acoustic transducers, particularlyultrasonic transducers, comprising

[0116] a sacrificial layer, and

[0117] a structural layer of insulating material,

[0118] rigidly connected to an upper surface of said siliconsemiconductor substrate, the surfaces of said sacrificial layer and ofsaid structural layer not in contact with said substrate beingsubstantially co-planar, said intermediate product being characterisedin that said structural layer comprises silicon monoxide.

[0119] Preferably according to this invention, said sacrificial layercomprises chromium.

[0120] Alternatively according to this invention, said sacrificialmaterial can comprise an organic polymer selected among the groupcomprising polyamides and polymers of benzocyclobutene and itsderivatives.

[0121] Preferably according to this invention, said organic polymercomprises polyamide.

[0122] Still according to this invention, said sacrificial layer andsaid structural layer have a thickness in the range of 100 nm to 1000nm, preferably in the range of 400 nm to 600 nm.

[0123] Again according to this invention, said intermediate product canfurther comprise a layer of resilient material having a Young's modulusno lower than 50 GPa, superimposed on said sacrificial layer (8) and onsaid structural layer.

[0124] Preferably according to this invention, said resilient materialof the intermediate product has a value of the Young's modulus no lowerthan 100 GPa.

[0125] Even more preferably according to this invention, said resilientmaterial of the intermediate product comprises silicon nitride.

[0126] Further according to this invention, said resilient material ofthe intermediate product can comprise crystalline silicon.

[0127] Still according to this invention, said layer of resilientmaterial can have a thickness no higher than 1000 nm, preferably nohigher than 600 nm.

[0128] The process according to this invention is innovative both inrespect of the utilised materials and in respect of the implemented stepset. The technologic process utilised a maximum temperature no higherthan 600° C., thereby enabling an extremely high design flexibility tobe obtained together with the direct integration of control electronicson the chip.

[0129] During the process development, the inventors have addressed anumber of problems. First of all, the implemented techniques and theconventional materials employed therein did not enable a structurallyintegral device to be obtained. The transducer became useless due todetachment and breakage of its structural layers, which were subject tohigh intrinsic stresses. Furthermore, all conventional materials asutilised therein did not offer any possibility to apply highly selectivechemical etching procedures.

[0130] The solution of such problems, therefore, enables mechanicallyvalid transducers to be obtained. Use of a special polymer has beenintroduced, polyamide, in substitution for the more conventional siliconcompounds. In the second place, the analysis of the chemical-physicalcharacteristics of the materials and their reaction to thermaltreatments enabled to determine the necessary durations and temperaturesfor the obtainment of films, with moderate and not destructive stresses.Lastly, it has been possible to strenghten the structure by designing aspecial geometrical shape that, by avoiding a concentration of thestresses to restricted areas of the film, made it possible to uniformlydistribute such stresses thereby preventing any weakness point fromestablishing.

[0131] In summary, the utilised techniques and novel material made itpossible to realise a structurally integral device having all desiredmechanical properties. The obtained device has been successfully testedboth in respect of the electrical impedance measurement and in respectof the acoustic signal measurement in reception-transmission.

[0132] The process according to this invention has been developed bysuccessfully experimenting the pre-patterning technique for effectivelycontrolling the geometry of the transducer components. In particular,the electrostatic cells were preliminarily shaped in order to achieve anoptimum control of the dimensional and geometric features of theindividual cells. Novel and not conventional materials never previouslyexploited in the micromanufacture field have been utilised in thisprocess. Particular relevance is to be attributed to utilisation of lowtemperature evaporate silicon monoxide as a structural layer to form theside supports of the membranes, also designated hereinafter as “rails”.In view of the low temperature deposition technique, it is perfectlycompatible with the photoresist as needed for the subsequent liftingremoval or simply lift off operation, as well as with the organicmaterial utilised as sacrificial layer. On the other hand, the lift offtechnique offers simplicity and unexpensiveness advantages in theprocess exploitation. The polyamide utilised as sacrificial layerenables an exceptional chemical etching selectivity to be obtained inrespect of the material by which the transducer is made, therebyallowing to maintain the characteristic properties of the structurallayers. The mechanical properties of the silicon nitride film grown by aPECVD technique appear to be easier to be controlled. A particulartechnique has been established to remove the sacrificial layer in ordernot to cause the adhesion of the structural layer to the substrate(stiction).

[0133] Electrical impedance measurements have been carried out on the sorealised devices and a mechanical resonance in the air at 5 MHz has beenevidenced.

[0134] In conclusion, the characteristics of the process according tothis invention are the realisation of a pre-patterning procedures forthe cavities, the utilisation of silicon monoxide to form the rails, theutilisation of a PECVD reactor for deposition of the layer that formsthe membranes and the utilisation of chromium or of a polymer, namely apolyamide, as a sacrificial layer, which enable to planarise the surfaceupon which the silicon nitride will be subsequently deposited. By thesefeatures the presence of a not planar membrane structure, withconsequent easy breakage at the edges, are avoided. The pre-patterningstep is very important because if offers a valid stoppage to thechemical attack, or etch stop, on releasing the membranes and thechromium or the polymer are easily workable by the usualmicromanufacturing techniques on silicon. The high process versatilityis made possible in view of the fact the chemical etch utilised forremoval of the chromium or the polymer, offers a 100% selectivity inrespect of the utilised materials, such as the silicon nitride, thesilicon monoxide and the silicon itself. By this procedure, thematerials by which the transducer will be effectively made are in no waydeteriorated, thereby maintaining all their quality levels in respect ofstrength and density. The apertures or vias for etching the sacrificiallayer are realised by means of a lithographic process and are optimisedso as to be subsequently closed in the final stage again by means of alithographic process.

[0135] A close study of the stresses under which the silicon nitride isgrown in the PECVD reactor and thermal treatments have been designed tocontrol such stresses, in order to realise membranes having the desiredmechanical properties to optimise the performances of the transducer.The analysis of the stress has further been performed by consideringthat silicon monoxide is utilised as support for the silicon nitride, sothat the mechanical interactions between these two materials, that arein reciprocal contact during the annealing procedure, have beeninvestigated.

[0136] A further result achieved by this invention in that a capacitivetransducer cMUT of a new kind has been realised, comprising an array ofsuitably parallel to one another connected, electrostatic cells, havingan interelectrode spacing noticeably reduced with respect to the cMUTtransducers of the previous generations. This result has been madepossible by realising the lower metallisation of the device on the upperside of the starting substrate just under the cavities and themembranes, thereby enabling the distances between lower and upperelectrodes to be reduced by an amount substantially equal to thesubstrate thickness. In view of this reason, a novel technologic processhas been designed for manufacturing a transducer adapted to operate inmore efficient manner and at higher frequencies as well as with reducedparasitic capacitances in comparison to previously realised devices.

[0137] As an example of design flexibility offered by this technology,the possibility to realise electrostatic cells having even relativelylarge dimension, aimed at realising a single array with components ofdifferent dimensions is to be mentioned. This technique enables to carryout a simultaneous scanning operations on layers arranged at differentdepths as well as the three-dimensional reconstruction in real time ofthe ecographic image, even if the application of the transducersaccording to this invention is not exclusively restricted to this field.

[0138] This invention will be now described by way of illustration, notby way of limitation, according to its preferred embodiments, byparticularly referring to the Figures of the annexed drawings, in which:

[0139]FIGS. 1A-1N show the steps carried out in a first preferredembodiment of the method according to this invention;

[0140]FIGS. 2A-2F show six mask typologies as utilised for definition ofthe membranes in the process according to FIGS. 1A-1N;

[0141]FIG. 3 is an upper plan view of the silicon semiconductorsubstrate as utilised in the process according to FIGS. 1A-1N;

[0142]FIG. 4 is a three-dimensional view of a detail of FIGS. 1E and 1F;

[0143]FIG. 5 is an upper plan view and a cross-section view of thedetail of FIG. 4;

[0144]FIG. 6 is a three-dimensional view of the detail of FIG. 4 afterchemical treatment;

[0145]FIG. 7 is an upper plan view and a cross-section view of thedetail FIG. 6;

[0146]FIGS. 8A-8C show the steps carried out in stage B of a secondpreferred embodiments of the process according to this invention;

[0147]FIG. 9 shows a diagram graphically representing the compressionstress of the membranes manufactured by the process according to thisinvention;

[0148]FIG. 10 shows a diagram graphically representing the absorptionspectrum of the membranes manufactured by the process according to thisinvention;

[0149]FIG. 11 is a three-dimensional view of a membrane manufactured bythe process according to this invention;

[0150]FIG. 12 is an upper plan view and a cross-section view of themembrane of FIG. 11;

[0151]FIG. 13 is an upper plan view and a cross-section view of amembrane manufactured by the process according to this invention atthree successive times;

[0152]FIGS. 15A-15N show the steps carried out in a third preferredembodiments of the process according to this invention;

[0153]FIG. 16A shows a first pattern utilised for realising the lowermetallisations in the process according to FIGS. 15A-15N;

[0154]FIG. 16B shows an enlarged portion of the pattern of FIG. 16A;

[0155]FIG. 17A shows a second pattern utilised for realising the lowermetallisations in the process according to FIGS. 15A-15N;

[0156]FIG. 17B shows an enlarged portion of the pattern of FIG. 17A;

[0157]FIGS. 18A-18E show images of first intermediate products obtainedduring the process of FIGS. 15A-15N as observed by an opticalmicroscope;

[0158]FIGS. 19A-19E show images of second intermediate products obtainedduring the process of FIGS. 15A-15N as observed by an opticalmicroscope;

[0159]FIGS. 20A-20D show the images of a device realised by the processof FIGS. 15A-15N as observed by an optic microscope;

[0160]FIGS. 21 and 22 show a view of the AFM of a membrane manufacturedby the process according to FIGS. 15A-15N at two successive times.

[0161] In the following description, the same reference numerals will beused to designate the same elements in the Figures.

[0162] In a first preferred embodiment of the process according to thisinvention, 340 devices corresponding to twelve different geometries aremanufactured on a single wafer. The realisation of a so large number ofdevices per wafer is possible in view of the fact that each device has asurface area of only 3 mm².

[0163] The circular shape of each individual electrostatic cell has beenselected since this shape optimises the characteristics of the generatedacoustic ultrasonic filed to the best.

[0164] In Table 1, the main geometrical characteristics of the twelverealised typologies are shown.

[0165] The process according to this invention starts from a siliconwafer grown according to the Czochralski methods, or CZ silicon, p-typedoped with boron (density: 10¹⁷ cm⁻³), having a resistivity of about 0.1Ω.cm with crystallographic orientation <100>. The side of the wafer onhe process is carried out is lapped. TABLE 1 Rail minimum Number ofMembrane Diameter of dimension Membranes diameter Type of vias vias Type(10⁻⁶ m) per device (10⁻⁶ m) arrangement (10⁻⁶ m) 1 10 1512 40 A 6 2 101512 40 B 4 3 10 1512 40 C 8 4 10 1512 40 D 4 5 10 1512 40 E 4 6 10 151240 F 4 7 10 1512 50 A 6 8 10 1512 50 B 4 9 10 1512 50 C 8 10 10 1512 50D 4 11 10 1512 50 E 4 12 10 1512 50 F 4

[0166] The first step to be carried out is the application of apolyamide layer which will subsequently suitably etched in order torealise the layout that should receive the support rails of thestructural layer. The polyamide layer forms the sacrificial layer andits thickness identifies the distance by which the membrane will bespaced from the substrate upon being released therefrom.

[0167] In particular, the polyamide represents the end treatment stageof a monomer solution that is applied to the wafer by means of a highspeed centrifugation technique or spinning. Two successive thermaltreatments are subsequently carried out in order to promote thepolymerisation reaction which results into a product designated aspolyamide.

[0168] The thickness of the layer depends on the rotation speed anddecreases after the polymerisation process is completed.

[0169] The polyamide utilised herein (N-methyl-2-pyrrolidone) is apolymer manufactured by Olin Microelectronic Materials having trade nameProbimide 112A selfpriming cat 851089.

[0170] The preliminary treatment of the wafer comprises a cleaning stepto remove the atmospheric dust, performed by putting the wafer under ajet of deionised running water and then drying it by a jet of nitrogen.More adherent particles are removed by imaging the sample into anacetone bath in a tank run through by ultrasonic waves, in order toexploit the cavitation effect. A cleaning operation particularly aimedat removal of organic residuals and fat acids can be carried out byimmersion into a bath formed by a solution comprising 70% sulphuric acid(H₂SO₄) and 30% hydrogen peroxide (H₂O₂).

[0171] After rinsing and drying the sample, a last dry cleaning step canbe carried out by utilising oxygen plasma.

[0172] All water residuals, which could jeopardise the adhesion of thepolymer to the surface, could be removed by means of a drying stepcarried out by heating the wafer in a furnace at 150° C. for 20 minutes.

[0173] The wafer in then arranged on the circular plate which thespinner is provided with, about 3 ml polyamide are put at the centralarea of the plate and this plate is then rotated, initially at lowspeed, until the polyamide reaches the edge of the wafer, then speed isincreased up to 4000 rpm during a total time of 120 seconds. The soprepared wafer is then treated in a furnace at a temperature of 120° C.for 30 minutes, in order to evaporate the solvents having the monomersdissolved therein. The last preparation stage of the layer to besubsequently utilised as a sacrificial layer consists in thepolymerisation process. The sample is arranged upon a quartz support inhorizontal position within a metal wall furnace, immersed in a nitrogenflow. The thickness measured after the polymerisation stage is about 890nm, which is higher than the 500 nm limit as required by thespecifications of the preferred embodiment of the process. A thinningstage should subsequently be carried out by means of a dry etchingoperation in RIE with a CF₄ flow rate of 12.6 sccm (standard cubiccentimetres per minute), an O₂ flow rate of 60 sccm, under a pressure of5.3 Pa, a power of 100 W and a via voltage of 200 V: the removal rate isfound to be 2.5 nm/s.

[0174] The lower electrode of the reactor should be protected by meansof a large silicon wafer, because it enables a higher etching spatialuniformity to be achieved. The etching time is of about 150 s.

[0175] The product obtained at the end of the above operations is shownin FIG. 1A where the substrate 1 and the polyamide layer 2 cm can beobserved.

[0176] The pre-patterning operations consist in etching the polyamidelayer 2 in order to form islands corresponding to the membranes thatform the sacrificial layer. The etching procedure is carried out as adry etching operation in a suitable plasma, by utilising an opticalresist as a masking layer. A positive photolithographic process isutilised in order to define the areas to be etched away in the polyamidefilm.

[0177] The mask utilised in the optical lithographic process is realisedby means of an electronic lithographic process. It is possible torealise on the same mask six different device typologies in respect ofthe via arrangement, as it is shown in FIGS. 2A-2F.

[0178] The typology of FIG. 2A is designed to realise a single via foreach membrane 3 at its centre area and it is almost designed tomanufacture a process control device. The other typologies provide forrealising the vias outside the circular membrane 3, in order to disturbthe circular geometry to the minimum possible extent. As regards thetypologies shown in FIGS. 2B, 2D and 2E, the vias are positioned withinthe outwardly protruding lunettes 4. In the typology of FIG. 2F the viasshould be arranged in order to be superimposed on the thin channels 5protruding from membrane 3.

[0179] The typology of FIG. 2C provides for arranging the vias 6completely outwardly of membrane 3 and the chemical etch of thesacrificial layer reaches the area corresponding to membrane 3, namelythe air gap, through the connection channels 7. This geometry inaddition to being scarcely perturbative enables optimum results to beobtained particularly at the stage in which the vias are to be closed,since the filling of the vias is not critic to membrane vibration,because it is sufficiently spaced apart and not tangent as in the othertypologies.

[0180] A frame for separating the 340 transducers has been realised inorder to aid performing the final cutting operations. The frame layoutis shown in FIG. 3, where the devices with membranes of 40 μm diameterhave been realised in the upper half section, while the devices withmembranes of 50 μm diameter have been realised in the layer halfsection.

[0181] At the end of the pre-patterning stage, polyamide islands havingthe shapes illustrated in FIGS. 2A-2F are obtained. By referring to FIG.1B, polyamide islands 8 can be observed, such islands being protected byoptical resist masks 9, between which the layout 10 that will be filledby rails of silicon monoxide has been etched. The etching operation ofthe polyamide takes place in RIE in order to obtain a more verticalremoval with respect to the wet etching operations. The etchingoperation is carried out with a formulation as already defined inconnection with the thinning stage of the polyamide.

[0182] The etching time for removing 480 nm of polyamide is of about 156s and it should be carefully controlled, because this formulationentails a silicon removal and, therefore, the risk to etch the substrateis run. The thickness control is effected by means of a profilometer.The optical resist masks 9 are not removed.

[0183] The rails are realised by thermally evaporated silicon oxide. Thechoice of this material is suggested by the fact that, since a materialis to be deposited upon the optical resist in view of the subsequentlift off step, it is necessary to carry out a low temperature process inview of the scarce heat resistance of such material. No particulartreatment of the wafer is carried out before evaporation of the siliconoxide, besides the usual removal operation of the dust particles indeionised water and in nitrogen flow. The thickness of the evaporatedsilicon oxide depends on the polyamide thickness existing on the sample,because both the oxide and the polyamide are to be levelled in order toobtain as much planar membranes as possible. The deposited thickness isequal to 500 nm.

[0184] After this stage is completed, the situation is as shown in FIG.1C, in which the rails 11 of silicon monoxide and the silicon monoxideareas 12 overlapping the optical resist masks 9 are shown.

[0185] The subsequent step provides for removing the silicon monoxideareas 12. The sample is immersed in acetone in order to dissolve theresist masks 9 by removing then the superimposed monoxide areas 12.

[0186] The amount of silicon monoxide to be removed is noticeable and,therefore, a good resist dissolution efficiency is necessary. A detailof FIG. 1C is shown in FIG. 1D to evidence that etching of resist byacetone starts from side direction. Therefore, it is necessary that thethickness of said resist masks 9 be sufficient, in respect of themonoxide amount to be evaporated, not to allow the side of said masks 9to be covered. However, should the vertical side of the concerned resistbe completely covered by monoxide, it would anyway be possible to removeit by other techniques.

[0187] After a few minutes of treatment with acetone, possibly withultrasonic aid, the situation shown in FIG. 1E is reached.

[0188] The enlargement illustrated in FIG. 1F shows the unavoidablemonoxide residual 13, also called “bind wing”, remaining at themonoxide-polyamide interface. This is a typical secondary effect of thistechnique and it is undesired in view of the fact that it represents abreakage point for the membrane to be superimposed to it.

[0189]FIG. 4 illustrates the three-dimensional reconstruction of themonoxide-polyamide interface profile based upon a surface scan obtainedby means of an atomic force microscope or AFM.

[0190]FIG. 5 illustrates the cross-section of the same profile and themeasurement of the differences in height existing between the polyamideisland 8, the monoxide rail 11 and monoxide residual 13.

[0191] Aiming at reducing the defects existing at the edges, it issuggested to operate with a wet etching operation in 5% solution ofhydrogen fluoride (HF). The immersion time is very short, about 2 s,because the silicon monoxide forming the rail member 11 should not beetched away.

[0192] Aiming at protecting the polyamide in respect of the hydrogenfluoride, the immersion is performed before carrying out the lift offoperation by means of an acetone bath, in order that the resist layerand the silicon oxide protect the underlying polyamide. This measurefurther improves the resist dissolution rate and accuracy in thesubsequent acetone bath, because the vertical sides will be more exposedto the etching solution.

[0193] By referring to FIG. 6, it can be observed that the wet etchingoperation nearly completely eliminates the bind wing formation 13, butit generates a groove 14 caused by penetration of the hydrogen fluorideto the monoxide-polyamide interface.

[0194] As it is shown in FIG. 7, the depth of the groove is not amenableto raise problems because the 500 nanometres of silicon nitride to bedeposited thereon will be sufficient to fill it up.

[0195] The drawback caused by said groove is overcome in a secondpreferred embodiment of this invention, in which the stage providing forrealisation of the intermediate product comprising polyamide islands 8and silicon monoxide rails 11 is different from the one described byreferring to FIGS. 1A-1E. By referring to FIGS. 8A-8C, it can beobserved that said rails 11 are deposited before depositing saidsacrificial polyamide, by means of a carpet deposition process extendedto the whole wafer, followed by pattern definition by means of a plasmaetching operation (FIG. 8A). Polyamide is subsequently deposited tocover the wafer (FIG. 8B) the liquid phase deposition and the subsequentpolymerisation or curing operation make the surface profile gradual, butsill sufficiently conforming to the underlying topography relating tothe monoxide rails 11. Lastly, a planarisation step is carried out bymeans of a chemical-mechanical polishing operation, by utilising asilica particle solution in alkaline environment, by rubbing the waferagainst a hard surface, preferably a glass surface. The surface turnsout to be completely planarised at the end of the polishing procedure,without formation of grooves at the edges of the rails 11 (FIG. 8C).

[0196] By referring to FIG. 1G, it can be observed that layer 15, bywhich said membranes are formed, is realised by silicon nitridedeposited by utilising a PECVD reactor. The thickness of the depositedfilm is of about 500 nm. A good adhesion is achieved between the siliconnitride and the monoxide. A preliminary cleaning operation is carriedout in acetone for 300 s followed by rinsing in deionised water.

[0197] In comparison to films grown by a LPCVD procedure, a PECVDprocedure enables films to be deposited at low temperatures, lower than400° C., and with mechanical characteristics variable within an extendedrange. The deposition of films of high quality at low temperaturesallows to utilise, for the sacrificial layer, materials that can beremoved very rapidly and with very high selectivity in respect ofsilicon nitride, such as polyamide or optical resist.

[0198] The control of the growing parameters of the silicon nitridefilms is essential for the obtainment of efficient membranes.

[0199] Laboratory tests have evidenced the problem of the mechanicalcompression stress of the silicon nitride films grown by means of aPECVD reactor. It was not possible to directly grow a silicon nitridefilm affected by tensile stress. The growing parameters adapted tominimise the compression stress are shown in Table 2. TABLE 2 RFFrequency 13.56 MHz Power 10 W Temperature 650 K Pressure 70 Pa Silaneflow 11 sccm Nitrogen flow 170 sccm Helium flow 220 Sccm

[0200]FIG. 9 shows a diagram of the compression stress behaviour as afunction of the silane/nitrogen ratio according to the measurementsaffected.

[0201] When the flow rate of silane is decreased with respect to theflow rate of nitrogen, a reduction of the compression stress can beobserved. The large amount of nitrogen in the film, however, makes thefilm more fragile.

[0202] The mechanical stress in the membranes can be modified by meansof heat treatments carried out after the film deposition. Heating thesilicon nitride to temperatures higher than 500° C. causes thickening ofthe film due to hydrogen desorption with formation of linkages betweensilicon and nitrogen. The reduction of the linkages Si—H (about 2100cm⁻¹) clearly appears from the absorption spectrum of FIG. 10. Thisspectrum is obtained by infrared spectroscopy or FTI, and it resultsfrom subtraction of the absorption of a silicon sample with 400 nmnitride and of the absorption of a clean silicon sample. The noiseencountered in connection with wave numbers higher than 2200 cm⁻¹ is dueto variations in air absorption between the acquisitions.

[0203] By referring to FIG. 1H, the holes through which the etchingoperation of the silicon nitride is carried out by means of a RIEetching procedure, aimed at realising the vias 16, are defined by asubsequent lithographic operation. In particular, the etching operationis carried out with a CHF₃ flow rate of 50 sccm, an O₂ flow rate of 8sccm, a pressure of 7.1 Pa, a power of 180W and a bias voltage of 260 V:the removal rate of the silicon nitride 15 turns out to be 0.67 nm/s,while the removal rate of the optical resist 17 is of 0.5 nm/s.

[0204] The etching time to realise a through hole in a standard membraneof 500 nm is of about 600 s, but aiming at assuring that said vias 16reach the sacrificial layer 8, such duration is extended to 900 s,without causing any damage, also keeping in mind that said sacrificiallayer will be eventually removed.

[0205] It is subsequently proceeded to a membrane releasing step. Byreferring to FIG. 1J, at the end of the polyamide sacrificial layer 8removal, the silicon nitride membranes 18 are suspended on an air gap 19of 500 nm and are sustained by rails 11 of silicon monoxide. Thechemical etching step on the polyamide is carried out preferably byimmersion in a 7:3 solution of sulphuric acid (H₂SO₄) and hydrogenperoxide (H₂O₂) that strongly attacks any compound, particularly thepolyamide, by means of a highly exothermal reaction, rapidly reaching353K. The selectivity in respect of silicon nitride, silicon oxide andsilicon itself amounts to 100%.

[0206] The complete removal of the sacrificial layer is carried out injust 2400 s time and the 100% selectivity assures a perfect integrity ofthe silicon oxide and silicon nitride films.

[0207] Should no heat treatment be carried out, the intrinsiccompression stress under which the PECVD nitride grows immediatelyappears on releasing the membranes. The effect observed is a camber inthe membrane due to the fact that the silicon nitride film has atendency to increasing its surface and the membranes engaged with therail have a tendency to explode upwardly. The circular geometry of thecells, the arrangement of the holes, the dimensions of the membranes andthe treatments carried out after the lift off operation synergisticallycontribute not to fragment the membrane even under a compression stress.FIG. 11 shows the three-dimensional reconstruction effected by said AFMfor a membrane according to typology of FIG. 2C, subjected to acompression stress after release, which makes it cambered upwardly.

[0208]FIG. 12 shows the cross-section of the membrane of FIG. 11: thecamber of the membrane is of about 1 nm which, when compared to 40 nmdiameter of the membrane, does not appear to be so relevant. Anyway, inview of assuring a correct operation of the transducer, a tensile stressappears to be preferable with respect to a compression stress.

[0209] When membranes having a higher Young's modulus are desired, byincreasing the silicon amount contained in the nitride film, an increasein the compression stress is obtained, which could cause breakage ofmany membranes.

[0210] In the preferred embodiment of the process according to thisinvention, the stress is gradually relieved by means of thermaltreatments in which the sample is heated to a temperature in the rangeof 490° C. to 530° C., preferably a temperature equal to 510° C.

[0211]FIG. 13 shows the variation of the membrane profile achieved bysubjecting the concerned device to two thermal annealing treatments,each extended to a 5 hour duration. The first annealing treatment iscarried out before the removal of the polyamide sacrificial layer,thereby reducing the compression stress and also making it notdestructive during the release step of the membranes.

[0212] In particular, the duration of the first thermal treatment can besuch as to completely consume the polyamide material, thereby making theremoval to be effected by chemical etching redundant. Further thermaltreatments can be carried out in order to further reduce the intrinsiccompression stress and to introduce an intrinsic tension stress intomembranes.

[0213] Furthermore, the annealing treatments allow to achieve a veryhigh design flexibility, also in terms of geometry and dimensions of themembranes.

[0214] After release of the membranes, the vias can be closed by meansof a silicon monoxide deposition, having a thickness equal to thethickness of the air gap 19, and of an optical lithography operation.Lastly, a metallisation of both sides of the wafer is carried out.

[0215] By referring now to FIG. 1K, it can be observed that the closureof the vias takes place as a column filling thereof by utilising siliconmonoxide that forms the stoppers 22. The thickness of the monoxide layer20 as deposited ought to be sufficient to form stoppers 22 reaching theunderlying nitride 18. In view of the above, it is necessary to depositat least a thickness equal to the air gap 19, which means 500 nm, in thepreferred embodiment, and, obviously a higher thickness is usuallydeposited for safety reasons, equal to 700 nm. The deposition techniqueis a low temperature evaporation based upon heating by Joule's effect acrucible containing silicon monoxide grains.

[0216] By referring to FIG. 1L, the monoxide layer 20 deposited onmembranes 18 should be removed because otherwise it would not allow acorrect operation of the transducer. The removal is carried out by meansof an optical lithographic operation with subsequent etching operationin RIE. The optical lithographic procedure is needed because it is.necessary to create a mask layer 21 consisting of an optical resist,suitably shaped in order to protect said stoppers 22 from the etchingagent acting on the silicon monoxide, leaving the monoxide 20superimposed to the membrane 18 exposed. Preferably, the thickness ofthe resist is 1.5 nm. Etching of the silicon monoxide is carried out inRIE according to the formulation already discussed in respect of theetching operation performed on silicon nitride for realising the vias.It is necessary to remove 700 nm of silicon oxide and, therefore,considering that the etching rate is of about 0.8 nm/s, the etching timeis of about 875 seconds. The utilised formulation slowly removes alsosaid optical resist, but this does not raise any problem, because it hasa endurance well beyond the duration of the etching operation.

[0217] The utilised formulation is not selective in respect of theunderlying silicon nitride, so that, during the etching operation, it isnecessary to control the oxide removal status, in order to stop theprocedure as soon as it is finished.

[0218] Subsequently, the residual resist is removed by an oxygen plasmain RIE, under an O₂ flow rate equal to 67 sccm, a pressure equal to 5.3Pa, a power equal to 100 W and a bias voltage equal to 200 V.Alternatively, the sample can be immersed in acetone for a few minutesand then rinsed in deionised water. At the end of the resist removaloperation, the product shown in FIG. 1M is obtained.

[0219] Should it be desired to make the electric control of thetransducer possible, it will be necessary to metallise the membranes 18and the back surface of the wafer 1.

[0220] By referring to FIG. 1N, the back surface of the wafer ismetallised by deposition of an aluminium film 23 of 150 nm thickness.The surface to be metallised is of not-lapped silicon. Such surfaceshould be cleaned and not oxidised, in order to guarantee a goodadhesion of the film as well as a good ohmic contact. At the end of theprocess, the wafer is heated to 650K for 1800 seconds in order toimprove the ohmic contact, in a steel furnace, under a nitrogen flowrate of 30 sccm.

[0221] On the other side of the wafer 1, aiming at reducing theparasitic capacitances of the transducer, only membranes 18 aremetallised. Only connections between the electrodes are providedcorresponding to the rails 11, while the contact with the externalcircuit is realised by means of a suitable pad. The metallisationpattern is realised by means of an optical lithographic process, withutilisation of a mask realised by an electronic lithographic process.The aluminium film applied for metallisation of the membranes isdeposited by sputtering. The metal layer patterning operation is carriedout by means of a further optical lithographic process, with utilisationof a mask realised by means of an electronic lithographic process,thereby obtaining the metallisation areas 24 of the membranes 18.

[0222] In a third embodiments of the process according to thisinvention, by referring to FIG. 14 to 22, the main improvements areconnected with utilisation of new materials to realise the lowermetallisation and the sacrificial islands of the transducer.

[0223] For realisation of the lower electrodes, it is suggested toutilise chromium as conductive material rather than aluminium, as alwaysutilised in the prior art devices, even if chromium has a resistivity of12.7×10⁻⁸ Ω.m. Such choice is determined by the fact that aluminium isnot adapted to withstand the deposition temperatures of the subsequentlayers which the device consists of. Furthermore, aiming at reducing theparasitic capacitances established in the transducer, the chromium layeras deposited is suitably patterned by means of an optical lithographicprocess, in order to obtain a structure exclusively entailing themetallisation of a restricted area corresponding to the cavities orhollow chambers and to the membranes. The upper metallisation isrealised by deposition of an aluminium layer, rather than chromium, inview of the fact that the latter would grow with a highly tensilemechanical stress, which sometimes could be destructive for themembranes. The aluminium film is subsequently treated in order to definethe metallised areas on the membranes and their interconnections,positioned with a complementary configuration with respect to theinterconnections of the lower metallisation, in order to limit theincidence of parasitic capacitances.

[0224] Another noticeable improvement is related to utilisation ofchromium as sacrificial material in substitution for the most commonsilicon compounds. The chemical etching operation utilised for itsremoval has a selectivity of 100% in respect of the other materialsutilised therein, such as the silicon nitride, the silicon monoxide andthe silicon itself, thereby assuring a perfect control of the activeregion of the transducer. In this way, the materials by which the devicewill be effectively formed are in no way deteriorated, therebymaintaining all their performances in respect of resistance and density.In fact, as it has been already evidenced, should a material having alow etching selectivity level with respect to the structural layers beutilised, also the membranes and the walls would be etched duringremoval of the sacrificial material, thereby modifying the dimensions ofthe cells and the thickness of the membranes themselves, with resultingvariation of the characteristic properties of the transducer.

[0225] Also in this third preferred embodiment, the pre-patterningtechnique is exploited by defining, by means of a photolithographicprocedure, the sacrificial islands before deposition of the membranes,in order to guarantee a micrometric definition of the device geometry.The hollow chambers or cavities upon which the membranes are suspendedeffectively represent the active regions of the transducer. Theirgeometry and dimension represent the main factors by which theperformances of the device are characterised.

[0226] In particular, FIG. 14 shows a microcell of the transducermanufactured by means of the third embodiment of the manufacturingprocess according to this invention. In this case, the lowermetallisation 25 is directly realised on the upper surface of the wafer,just under the membranes 18 and the corresponding cavities, therebyreducing the distance between stationary lower electrodes and the mobileupper electrodes by a thickness substantially equal to the thickness ofsubstrate 1, equal to about 380 nm.

[0227] The third embodiment of the manufacturing process according tothe invention utilises 3″ p-type doped silicon wafers, having aresistivity of about 0.1 Ω.cm with crystallographic orientation <100>.

[0228] A number of 340 devices are micromachined on a single wafer, eachof which is characterised by 1512 membranes. A so high number of devicesis made possible by the small area engaged by each of them equal to 3mm². Each membrane has a circular type shape realised by referring topolygons of 16 sides. Such a geometry perfectly matches thecharacteristics of the acoustic field generated. The individualmembranes appear to be arranged according to a configuration of amatricial type with a minimum distance of 10 nm from one another.

[0229] One half of the devices realised on the wafer are formed bymembranes each having a diameter of 40 nm, while the devices of theother half are formed by membranes having a greater diameter equal to 50nm.

[0230] As far as each device is concerned, reference is made toelectrostatic cells having geometric shapes realised, in respect of theholes provided for etching the sacrificial layer and the connectionbars, according to the five different typologies shown in FIGS. 2B, 2C,2D, 2E and 2F. In total there are ten different typologies realised byexploiting the two different dimensions of the considered membranes.

[0231] By referring to FIG. 15A, according to the third embodiment ofthe process of this invention, an insulating layer 26 of thermal silicondioxide SiO₂ is deposited to isolate the starting silicon substrate 1from the lower metallisation.

[0232] By referring to FIG. 15B, the process provides for realising thelower electrodes 25. The lower metallisation is realised by depositing auniform chromium layer by evaporation. The chromium film is subsequentlypatterned by means of an electronic lithographic process aimed atimparting a particular geometric shape to the lower metallisation. Theneed to reduce the parasitic capacitances of the transducer resultedinto metallisation of the membranes 18 only so that the connectionsbetween the electrodes 25 are realised by means of suitable conductivepaths realised in positions corresponding to the rails 11 and thethickness of which is not higher than 4 nm. The dimensions of theelectrodes 25 are selected to optimise the performances of thetransducer. They are exclusively realised in the central portion of eachmembrane 18 so as to increase the ratio between the capacitancemodulation and the static capacitance of the device. Due to this reason,the process realises electrodes 25 utilising only 60% of a surfacecorresponding to the surface of the membranes 18 and with a smallthickness if compared to the thickness of the membranes 18. Whenmembranes 18 having diameters of 40 μm and 50 μm are realised, theobtained electrodes 25 have diameters of 24 μm and 30 μm, respectively.

[0233] Connection pads are utilised to allow the realisation of anelectric contact between the electrodes 25 and the external circuit.

[0234] As it is shown in FIG. 15C, the pattern of the lower electrodes25 and of their related interconnections is protected by means of a film27 of silicon nitride SiN grown by means of a PECVD technique.

[0235] Subsequently, as it is shown in FIG. 15D, a film 28 of chromiumis deposited by means of an evaporation technique as a sacrificialmaterial.

[0236] By referring to FIG. 15E, pre-patterning of sacrificial islands8′ is carried out by means of an optical lithographic process, byutilising a suitable mask realised by means of an electroniclithographic process. A subsequent wet etching operation is carried outon said chromium in order to define the regions forming said island 8′.The chromium layer exclusively remains unaltered in regionscorresponding to the area by which the cavities (air gap) of thetransducer will be characterised. The above said layer 28 defines thethickness of the cavity in the transducer and, therefore, it is acritical variable in designing the performances of the transducers. Theresist (not shown) applied upon the islands 8′, which is not exposedduring the lithographic process, is not removed in order to permitexecution of the subsequent step of the process.

[0237] In particular, FIG. 18A, 18B, 18C and 18E show the opticalmicroscope images of the chromium sacrificial islands 8′ before themonoxide rails 11 are formed, respectively corresponding to the fivegeometric shapes of the etching holes shown in FIGS. 2B, 2C, 2D, 2E and2F.

[0238] By referring now to FIG. 15F, a layer of silicon monoxide SiO, isdeposited by means of an evaporation operation based upon the Joule'seffect, in order to realise a planar type structure and to create rails11 aimed at supporting the membranes 18. The excess monoxide grown uponthe islands 8′ is removed by means of a lift off process, by dissolvingthe resist not removed by the previous step, by acetone and ultrasounds.

[0239] The thickness of the deposited monoxide is equal to the thicknessof the sacrificial islands 8′ in order to obtain rails 11 having thesame height as the cavities. This enables a subsequent structural layerof the membranes 18 to be deposited upon a planar type surface, therebyassuring a uniform stress distribution in the membranes and avoidingpossible breakage points for the membranes themselves.

[0240] In particular, FIGS. 19A, 19B, 19C, 19D and 19E show the opticalmicroscope images of the chromium sacrificial islands 8′ after themonoxide rails 11 have been created, respectively corresponding to thefive geometric shapes of the etching holes shown in FIGS. 2B, 2C, 2D, 2Eand 2F.

[0241] By referring to FIG. 15G, the realisation of the membranes 18 iscarried out by depositing a layer 15 of silicon nitride SiN_(x) byexploiting a PECVD technique. The residual stress of the nitride film 15can be controlled by varying the plasma frequency, the substrate 1temperature and the nitrogen and silicon relative concentrations duringthe deposition process. The intrinsic stress in the silicon nitridemembrane 18 has been designed so as to have a scarce tensile characterby controlling the radio-frequency power in the PECVD process. Thethickness of the film 15 can be controlled in the PECVD process, aswell. The stress under which the film 15 is grown represents anessentially important factor in view of the fact that, as previouslydiscussed, the resonance frequency of the membrane 18 depends thereon.

[0242] A thermal annealing step of the sample is then carried out inorder to reduce the compression stress in the membranes 18, which wouldcause a subsequent camber effect as well as their breakage afterreleasing thereof, with conversion of the compressive stress into aweakly tensile stress.

[0243] By referring to FIG. 15H, it can be observed that submicrometricapertures 16 (etchant holes) are defined, by means of an opticallithographic process, on the membrane 18 area, in order to enablechromium to be subsequently removed from the underlying sacrificialislands 8′. The above mentioned apertures 16 are provided in perimetralpositions on each individual membrane according to five differenttypologies as shown in FIGS. 2B-2F, which assure an efficient etching ofsaid sacrificial islands 8′ as well as an excellent mechanical stabilityof the structure.

[0244] A mask with a pattern of holes 16 having a design diameter of 4nm is realised by means of an electronic beam lithographic process. Thedimensions of the vias 16 should be small, in order to enable the holesto be closed and the cavities be sealed, but, on the other hand, theyshould be sufficiently large as to enable the underlying sacrificiallayer to be removed.

[0245] The realisation of said silicon nitride vias 16 is carried out onthe silicon by means of a dry etching operation with a reactive ionetching (RIE) technique.

[0246] By referring to FIG. 15H, it can be observed that, upon openingthe vias 16 through the nitride layer 15, the sacrificial chromium layer8′ is removed by means of a suitable wet etching solution. This etchingoperation is isotropic and assures a 100% selectivity in respect of thestructural nitride and the monoxide SiO of rails 11. The above solutionpenetrates through holes 16 and removes the chromium underlying themembranes 18, thereby having them in suspended condition.

[0247] As it is shown in FIG. 15J, the product at this point consists ofa matrix of silicon nitride membranes 18 suspended on silicon monoxidesupports 11.

[0248] By referring to FIG. 15K, it can be observed that, upon releasingsaid membranes 18, the above vias 16 are closed by two successive steps:a silicon monoxide SiO deposition by means of an evaporation operationbased upon the Joule's effect, with a thickness equal to the thicknessof the cavities, and an optical lithographic step.

[0249] The vias 16 are closed by column filling them with the samematerial by which the rails 11 are formed. The thickness of the monoxidelayer 20 as deposited should be sufficient to form stoppers 22 extendedup to reaching the overlying silicon nitride layer 18.

[0250] The removal of the monoxide layer 20 deposited on said membranes18 is carried out by means of an optical lithographic process and a dryetching operation in RIE, thereby obtaining the product shown in FIG.15L.

[0251] The optical lithographic step allows to realise a masking layerof optical resist so shaped as to protect the above said stoppers 22 inrespect of the etching step carried out on the silicon monoxide and toleave the monoxide overlying the membranes 18 uncovered, in similar wayas shown in FIG. 1L.

[0252] It is necessary that said etchant holes 16 be closed, not only inorder to enable the concerned transducers to be utilised in immersedcondition, but also to protect the cavities from possible contaminationsthat could modify the vibration properties of said membranes 18, withresulting alteration of the performances of the concerned transducer.

[0253] Aiming at further improving the sealing of said vias 16, a thinfilm of silicon nitride SiN is preferably grown subsequently by means ofPECVD technique, which enables hermetic sealing of said vias 16, withoutsignificantly modifying the vertical dimension of the transducer.

[0254] The subsequent process step is aimed at realising the uppermetallisation.

[0255] A conductive layer of aluminium is deposited by a sputteringoperation. A subsequent deposition of a thin layer of titanium is thencarried out also by sputtering.

[0256] The pattern of the upper electrodes 24 and of the relatedinterconnections (not overlapping the lower interconnections) isrealised by means of an optical lithographic process, under utilisationof a mask realised by means of an electronic lithographic process.Aiming at reducing the parasitic capacitances of the transducer, onlysaid membranes 18 are metallised. Corresponding to rails 11 onlyconnections between electrodes 24 are provided in complementarypositions with respect to the connection paths of the electrodes 25 ofthe lower metallisation, in order to avoid useless overlaps and toreduce any possibly existing parasitic capacitances. The contact to theexternal circuitry occurs by means of a suitable pad.

[0257] The titanium layer in the exposed regions of the optical resistis then removed by means of a dry etching operation in RIE. Theunderlying exposed aluminium layer is removed by a wet etching operationin a suitable etchant solution, thereby obtaining the product shown inFIG. 15M.

[0258] In particular, the pads corresponding to the lower metallisationare opened by means of a lithographic process with related mask and bymeans of a dry etching operation in RIE aimed at removing the structuresilicon nitride SiN_(x) and the silicon monoxide layers.

[0259] By referring to FIG. 15N, the wafer is then covered by a thinprotection layer 28 of silicon nitride SiN_(x) grown by means of a PECVDtechnique, utilised for protecting the upper metallisation and to assurehermetic sealing of the cavities.

[0260] The pads are opened in order to enable the realisation of thecontacts to the measurement external circuitry, by means of an opticallithographic process, with utilisation of a mask realised by means of anelectronic lithographic process and a dry etching operation in RIE, forremoval of the protection silicon nitride SiN_(x) corresponding to thelower and upper pads.

[0261] In particular, FIG. 16A shows a first configuration as utilisedfor the lower metallisation clearly evidencing pad 29 for connection tothe external circuitry. FIG. 16B shows an enlarged portion of theconfiguration of FIG. 16A.

[0262] In similar way, FIG. 17A shows a second configuration as utilisedfor the lower metallisation, and FIG. 17B shows an enlarged portionthereof.

[0263]FIGS. 20A, 20B, 20C and 20D show optical microscope images of thefinished device, clearly evidencing the membranes 18, the rails 11, theetchant vias 16 and the lower electrodes 25 and upper electrodes 24.

[0264]FIG. 21 is an AFM view of a membrane 18 before the thermalannealing step, while FIG. 22 is an AFM of the same membrane 18 afterthe thermal annealing step.

[0265] The preferred embodiments of this invention have been describedand a number of variations have been suggested hereinbefore, but itshould expressly be understood that those skilled in the art can makeother variations and changes, without so departing from the scopethereof, as defined by the enclosed claims.

1. A surface micromachining process for manufacturing Electro-acoustictransducers, particularly ultrasonic transducers, said transducerscomprising a silicon semiconductor substrate (1), on an upper surface ofwhich one or more membranes (18) of resilient materials are supported bya structural layer (11) of insulating material, rigidly connected tosaid semiconductor substrate (1), said resilient material having aYoung's modulus not lower than 50 GPa, said membranes (18) beingmetallised, said transducers including one or more lower electrodes (23,25), rigidly connected to said semiconductor substrate (1), the processcomprising the following steps: A. providing a silicon semiconductorsubstrate (1), B. realising an intermediate product comprising: asacrificial layer (8, 8′), and a structural layer (11) of insulatingmaterial, rigidly connected to an upper surface of said siliconsemiconductor substrate (1), the surfaces of said sacrificial layer (8,8′) and of said structural layer (11) not in contact with said substrate(1) being substantially co-planar, C. depositing a layer (15) of saidresilient material on said sacrificial layer (8, 8′) and on saidstructural layer (11), and D. releasing said membranes (18) of saidresilient material by removing said sacrificial layer (8, 8′) from theproduct obtained according to said step C., said process beingcharacterised in that said structural layer (11) includes siliconmonoxide.
 2. A process according to claim 1, characterised in that allof the steps of the process are carried out at temperatures not higherthan 600° C.
 3. A process according to claim 2, characterised in thatall of the steps of the process are carried out at temperatures nothigher than 530° C.
 4. A process according to any one of the precedingclaims, characterised in that said resilient material has a value of theYoung's modulus not lower than 100 GPa.
 5. A process according to claim4, characterised in that said resilient material comprises siliconnitride.
 6. A process according to claim 4, characterised in that saidresilient material comprises crystalline silicon.
 7. A process accordingto any one of the preceding claims, characterised in that saidsacrificial material (8′) comprises chromium.
 8. A process according toany one of claims 1 to 6, characterised in that said sacrificialmaterial (8) comprises an organic polymer selected among the groupcomprising polyamides and polymers of benzocyclobutene and itsderivatives.
 9. A process according to claim 8, characterised in thatsaid organic polymer comprises polyamide.
 10. A process according toclaim 9, characterised in that said polyamide comprisesN-methyl-2-pyrolidone.
 11. A process according to any one of thepreceding claims, characterised in that said step D comprises thefollowing successively ordered sub-steps: D.1 realising one or moreapertures or vias (16) on said layer (15) of resilient material, adaptedto enable accessing the sacrificial layer (8) from outside, and D.2thermally treating by annealing the product obtained according to saidstep C.
 12. A process according to claim 9, characterised in that,during execution of said sub-step D.2, the product obtained according tosaid step C is heated to a temperature in the range of 490° C. to 530°C.
 13. A process according to claim 11 or 12, when considered asdependant on any one of claims 8 to 10, characterised in that saidsub-step D.2 has a duration adapted to completely eliminate the organicpolymer existing in the product obtained according to said step C.
 14. Aprocess according to any one of the claims 11 to 13, characterised inthat said step D further comprises, indifferently before or after saidsub-step D.1 or D.2, the following sub-step: D.3 chemically etching saidsacrificial layer.
 15. A process according to claim 14, when consideredas dependant on claim 7, characterised in that said sub-step D.3comprises imaging the product in a wet etching solution for etchingchromium.
 16. A process according to claim 14, when considered asdependant on any one of claims 8 to 10, characterised in that saidsub-step D.3 comprises imaging the product obtained according to saidstep C in a solution comprising sulphuric acid (H₂SO₄).
 17. A processaccording to claim 16, characterised in that said solution utilised insaid sub-step D.3 further comprises hydrogen peroxide (H₂O₂).
 18. Aprocess according to claim 17, characterised in that said solutionutilised in said sub-step D.3 is a solution 7:3 of sulphuric acid(H₂SO₄) and hydrogen peroxide (H₂O₂).
 19. A process according to any oneof claims 14 to 18, characterised in that, when said sub-step D.3 issubsequent to said sub-step D.2, said step b further comprises, aftersaid sub-step D.3, the following sub-step: D.4 thermally treating byannealing the product obtained according to said step D.
 20. A processaccording to claim 19, characterised in that, during execution of saidsub-step D.4, the product obtained according to said step C is heated toa temperature in the range of 490° C. to 530° C.
 21. A process accordingto any one of claims 11 to 20, characterised in that the total durationof the annealing operation for the product obtained according to saidstep C is adapted to make the intrinsic compression stress of themembranes (18) no higher than 10 MPa.
 22. A process according to claim21, characterised in that the total duration of the annealing operationfor the product obtained according to said step C is adapted to make theintrinsic tensile stress of the membranes (18) comprised in the range of10 MPa to 50 MPa.
 23. A process according to any one of the precedingclaims, characterised in that said vias (16) are external to thelocations of said membranes (18) and are positioned at a distancetherefrom adapted to introduce substantially negligible stressgradients, said sacrificial layer (8) comprising channels (7) to connectthe positions of said vias (16) to the locations of said membranes (18).24. A process according to claim 7, characterised in that said step Bcomprises the following successively ordered sub-steps: B.1 depositing achromium comprising layer (28) on said upper surface of thesemiconductor substrate (1), B.2 defining configurations or patterns insaid chromium comprising layer (28) by realising cavities in saidchromium comprising layer (28), and B.3 filling said cavities in saidchromium comprising layer (28) by depositing silicon monoxide therein.25. A process according to any one of the preceding claims 8 to 10,characterised in that said step B comprises the following successivelyordered sub-steps: B.1 applying a layer (2) comprising said organicpolymer upon said upper surface of the semiconductor substrate (1), B.2defining configurations or patterns in said layer (2) comprising saidorganic polymer by realising cavities (10) in said in said layercomprising said organic polymer, and B.3 filling said cavities (10) insaid layer (2) comprising said organic polymer by depositing siliconmonoxide therein.
 26. A process according to claim 24 or 25,characterised in that, during said sub-step B.3, the silicon monoxide isdeposited by thermal evaporation.
 27. A process according to claim 24 or26, when considered as dependant on claim 24, characterised in that saidsub-step B.2 comprises an optical lithographic process performed on saidchromium comprising layer (28) by utilising a masking layer ofphotographically patterned optical resist and a wet chemical etching ofthe chromium.
 28. A process according to claim 25 or 26, when consideredas dependant on claim 25, characterised in that said sub-step B.2comprises a dry reactive ion etching (RIE) operation performed on saidlayer (2) comprising said organic polymer by utilising a masking layer(9) of photolithographically patterned optical resist.
 29. A processaccording to claim 27 or 28, characterised in that said step B furthercomprises, after said sub-step B.3, the following sub-steps: B.4chemically etching said silicon monoxide by utilising a wet etchingprocess, B.5 removing said optical resist.
 30. A process according toclaim 27 or 28, characterised in that said step B further comprises,after said sub-step B.3, the following sub-step: B.4 removing thesilicon monoxide deposited upon said optical resist by means of a liftoff process.
 31. A process according to claim 30, characterised in thatsaid sub-step B.4 comprises dissolving said optical resist by means ofan acetone and ultrasound dissolving process.
 32. A process according toany one of claims 8 to 10, characterised in that said step B comprisesthe following successively ordered sub-steps: B.1 depositing a siliconmonoxide comprising layer on said upper surface of the semiconductorsubstrate (1), B.2 defining configurations or patterns (11) in saidsilicon monoxide comprising layer, B.3 applying a layer (2) comprisingsaid organic polymer upon said upper surface of the semiconductorsubstrate (1), provided with silicon monoxide, B.4 performing achemical-mechanical polishing operation adapted to realise saidintermediate product.
 33. A process according to claim 32, characterisedin that during said sub-step B.1, the silicon monoxide is deposited bythermal evaporation.
 34. A process according to claim 32 or 33,characterised in that said sub-step B.2 comprises a dry reactive ionetching (RIE) operation performed on said silicon monoxide comprisinglayer by utilising a masking layer of photolithographically patternedoptical resist.
 35. A process according to any one of the precedingclaims, characterised in that, during said step C, said resilientmaterial is deposited by a plasma enhanced chemical vapour depositionprocess (PECVD).
 36. A process according to claim 11, characterised inthat it further comprises, after said step D, the following step: E.closing said vias (16) by deposition of silicon monoxide adapted to fillup said vias (16), optical lithography, and RIE etching of the siliconmonoxide deposited on said membranes (18).
 37. A process according toclaim 36, characterised in that during said step E, the silicon monoxideis deposited by thermal evaporation.
 38. A process according to any oneof the preceding claims, characterised in that it further comprises,before said step B, the following step: F. realising a lower electrode(25) on the upper surface of the semiconductor substrate (1) inpositions corresponding to each area in which said membranes (18) arerealised during said step D.
 39. A process according to claim 38,characterised in that said step F comprises the following sub-steps: F.1depositing an insulating layer (26) on the upper surface of thesemiconductor substrate (1), F.2 depositing a conductive layer upon saidinsulating layer (26), F.3 defining configurations or patterns in saidconductive layer.
 40. A process according to claim 39, characterised inthat said insulating layer (26) comprises thermal silicon dioxide SiO₂,said conductive layer comprises evaporation deposited chromium, and saidsub-step F.3 comprises an optical lithographic process performed on saidconductive layer by utilising a masking layer formed by aphotolithographically patterned optical resist and a chemical wetetching of the chromium.
 41. A process according to any one of claims 38to 40, characterised in that said step F further realises a film (27)for protection of said lower electrodes (25).
 42. A process according toclaim 41, characterised in that said protection film (27) is realised bygrowing a film of silicon nitride SiN by means of a PECVD technique. 43.A process according to any one of claims 1 to 37, characterised in thatit further comprises the following step: F. realising one or more lowerelectrodes (23) by metallisation of a lower surface of saidsemiconductor substrate (1).
 44. A process according to any one of thepreceding claims, characterised in that it further comprises thefollowing step: G. metallising said membranes (18)
 45. A processaccording to any one of the preceding claims, characterised in that saidsilicon semiconductor substrate (1) is a p-type doped silicon substratehaving a resistivity no higher than 1 Ω.cm, preferably no higher than 2Ω.cm.
 46. A process according to any one of the preceding claims,characterised in that said silicon monoxide comprising structural layer(11) has a thickness in the range of 100 nm to 1000 nm, preferably inthe range of 400 nm to 600 nm, and in that said membranes (18) of saidresilient material have a thickness no higher than 1000 nm, preferablyno higher than 600 nm.
 47. An Electro-acoustic transducer, particularlyan ultrasonic transducer, comprising a silicon semiconductor substrate(1), on an upper surface of which one or more membranes (18) ofresilient materials are supported by a structural layer (11) ofinsulating material, rigidly connected to said semiconductor substrate(1), said resilient material having a Young's modulus not lower than 50GPa, said membranes (18) being metallised , said transducer includingone or more lower electrodes (23, 25), rigidly connected to saidsemiconductor substrate (1), said transducer being characterised in thatsaid insulating material is silicon monoxide.
 48. A transducer accordingto claim 47, characterised in that said resilient material has a valueof the Young's modulus no lower than 100 GPa.
 49. A transducer accordingto claim 48, characterised in that said resilient material comprisessilicon nitride.
 50. A transducer according to claim 48, characterisedin that said resilient material comprises crystalline silicon.
 51. Atransducer according to any one of claims 47 to 50, characterised inthat said membranes (18) have an intrinsic compression stress no higherthan 10 MPa.
 52. A transducer according to claim 51, characterised inthat said membranes (18) have an intrinsic tensile stress in the rangeof 10 MPa to 50 MPa.
 53. A transducer according to any one of claims 47to 52, characterised in that said silicon monoxide comprising structurallayer (11) has a thickness in the range of 100 nm to 1000 nm, preferablyin the range of 400 nm to 600 nm, and in that said membranes (18) ofsaid resilient material have a thickness no higher than 1000 nm,preferably no higher than 600 nm.
 54. A transducer according to any oneof claims 47 to 52, characterised in that said one or more lowerelectrodes (25) are realised on the upper surface of said semiconductorsubstrate (1) in positions corresponding to each of said areasunderlying said membranes (18).
 55. A transducer according to claim 54,characterised in that it further comprises an insulating layer (26),underlying said lower electrodes (25), on the upper surface of saidsemiconductor substrate (1).
 56. A transducer according to claim 55,characterised in that said insulating layer (26) comprises silicondioxide SiO₂ and said conductive layer comprises chromium.
 57. Atransducer according to any one of claims 54 to 56, characterised inthat it further comprises a film (27) for protection of said lowerelectrodes (25).
 58. A transducer according to claim 57, characterisedin that said protection film (27) comprises silicon nitride SiN.
 59. Atransducer according to any one of claims 47 to 53, characterised inthat said one or more lower electrodes are realised by means of ametallised layer (23) on said lower surface of the semiconductor layer(1).
 60. An intermediate product for realising Electro-acoustictransducers, particularly ultrasonic transducers, comprising asacrificial layer (8), and a structural layer (11) of insulatingmaterial, rigidly connected to an upper surface of said siliconsemiconductor substrate (1), the surfaces of said sacrificial layer (8)and of said structural layer (11) not in contact with said substrate (1)being substantially co-planar, said intermediate product beingcharacterised in that said structural layer (11) comprises siliconmonoxide.
 61. An intermediate product according to claim 60,characterised in that said sacrificial layer (8′) comprises chromium.62. An intermediate product according to claim 60, characterised in thatsaid sacrificial material (8) comprises an organic polymer selectedamong the group comprising polyamides and polymers of benzocyclobuteneand its derivatives.
 63. An intermediate product according to claim 62,characterised in that said organic polymer comprises polyamide.
 64. Anintermediate product according to any one of claims 60 to 63,characterised in that said sacrificial layer (8) and said structurallayer (11) have a thickness in the range of 100 nm to 1000 nm,preferably in the range of 400 nm to 600 nm.
 65. An intermediate productaccording to any one of the preceding claims, characterised in that itfurther comprises a layer (15) of resilient material having a Young'smodulus no lower than 50 GPa, superimposed on said sacrificial layer (8)and on said structural layer (11).
 66. An intermediate product accordingto claim 65, characterised in that said resilient material has a valueof the Young's modulus no lower than 100 GPa.
 67. An intermediateproduct according to claim 65 or 66, characterised in that saidresilient material comprises silicon nitride.
 68. An intermediateproduct according to claim 65 or 66, characterised in that saidresilient material comprises crystalline silicon.
 69. An intermediateproduct according to any one of claims 65 to 68, characterised in thatsaid layer (15) of resilient material has a thickness no higher than1000 nm, preferably no higher than 600 nm.